1. Field of the Invention
This invention relates to a processor, and especially to its architecture and its method of executing instructions. In particular, the invention relates to a processor that reads a multiple-byte instruction a byte at a time from a memory, assembles the bytes in a register, and then decodes and executes the instruction.
2. Description of the Related Art
In this type of processor, instructions are generally stored at ascending addresses as illustrated in FIG. 13, in which instruction i1 is stored at addresses j, j+1, j+2, and j+3, instruction i2 at addresses j+4, j+5, j+6, and j+7, and so on. When an instruction is read, its leading byte is indicated by an address pointer, and the succeeding bytes are indicated by an address counter. The bytes constituting the instruction are read sequentially into corresponding byte positions in an instruction register having sufficient capacity to store the entire instruction. When all bytes of the instructions have been read into the instruction register, the instruction is supplied to an instruction decoder and executed. When one instruction has been executed, the address pointer is altered to point to the leading byte of the next instruction, and the same process is repeated.
A problem with this procedure is that each time an instruction is executed, a new address pointer value must be generated, indicating the address of its leading byte. To execute a program including a large number of instructions, a large amount of address information is needed.
In some processors, a plurality of instructions are executed concurrently, but this requires a like plurality of address pointers, so the amount of information needed to execute a program is not reduced.